Low-cost 10Gb/s PRBS (patent pending) and further high-speed electronics available
The 10Gb/s PRBS generator core uses a novel approach in the linear-feedback shift register implementation (patent pending). The new implementation simplifies PRBS-core design and enables higher clock frequency at the same time. Therefore high-performance system was developed at a small fraction of the price of the brand commercial equipment. Pursuit of novel ideas and inovative designs will be the foundation of the spin-off entering the high-speed and high-frequency market of the future.
- 10Gb/s PRBS Generator
- High performance, very-low output-data jitter of <10ps-pp
- Pattern-length sync output
- Standalone unit including clock source
- Clock and clock/4 outputs
10Gb/s PRBS generator
 
Output-data eye diagram (left) and output-data bitstream (right)
- 10Gb/s Data Demultiplexers
- 10Gb/s to two 5Gb/s bitstreams
- 10Gb/s to four 2.5Gb/s bitstreams
- Low output-data jitter
- Includes clock recovery
- Includes loss-of-signal and loss-of-lock indication
 
10Gb/s data demultiplexer: 2x 5Gb/s (left) and 4x 2.5Gb/s (right)
- High-speed low-delay auto-locking phase detector for phase-locked loops
- Wide input frequency range (1GHz - 10GHz)
- Wide bandwidth (DC to several GHz)
- Wide phase-detector comparison frequency range (1GHz - 10GHz)
- Separate proportional and integrational paths
- Auto phase-locking capability upon power-up
- Extremely low delay (<1ns)
- Optimal for optical PLLs (mm-wave and terahertz signal generation)
- Low-noise and low-spurious output signal
High-speed low-delay phase detector
If you are interested in receiving more information please do not hesitate to contact us.
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